The present invention relates generally to an electrically erasable programmable non-volatile semiconductor memory device, in which a memory, comprising an electricity-charging floating gate electrode and a control gate electrode stacked thereon, is used as a memory cell, and more particularly to a NAND EEPROM (electrically erasable programmable ROM) in which a plurality of memory cells are connected in series.
FIG. 1A is a plan view showing one memory cell column of a conventional NAND EEPROM, and FIG. 1B is a diagram showing an equivalent circuit of the memory cell column shown in FIG. 1. FIG. 2 is a cross-sectional view of the memory cell column shown in FIG. 1A, taken along the line II--II. FIG. 3 is a cross-sectional view of the memory cell column shown in FIG. 1A, taken along the line III--III.
The memory cell column is formed in a double-diffusion type p-well 11 formed in a p-type semiconductor substrate. Each of the memory cells of the column has an electricity-charging floating gate electrode 14 and a control gate electrode 16. In the following description, the memory cell may be called simply a cell. As shown in the drawings, the memory cell column is constituted by a plurality of stacked-type memory cells M1 to M8 connected in series and controlled by control gates CG1 to CG8. Selection transistors S1 and S2 are respectively provided on both ends of the serially-connected memory cell column, i.e., on both a drain D side and a source S side. Selection gates SG1 and SG2 of the selection transistors S1 and S2 control the connection or disconnection between a bit line 18 of the memory cell column on one hand and a common source line on the other. In FIG. 3, a reference numeral 17 denotes an interlayer insulating film. In FIG. 2, elements 14.sub.9 and 14.sub.10 are electrically connected to each other, and elements 16.sub.9 and 16.sub.10 are electrically connected to each other in a region (not shown) to form the selection gate SG1 and SG2, respectively.
FIG. 4 shows voltages applied to the respective portions in erasing, writing and reading operations in the memory cell described above. The operations and problems thereof will be described below.
Data Erasing
To erase data, a bit line BL and a source S are opened, the control gate CG and selection gates SG1 and SG2 are all biased to 0V and an erasure voltage V.sub.EE (e.g., 20V) is applied to the substrate W (p-well layer) 11. As a result, the tunneling of an oxide film is effected. Utilizing the tunneling effect, electrons in all the floating gate electrodes are extracted. Consequently, the threshold voltages of all the memory cells are 0V or lower, resulting in that the memory cells are in a normally-on state (depletion type). In this description, the normally-on state is defined as data "1". On the other hand, a normally-off state (enhancement type) is defined as data "0".
When data is collectively erased in the conventional NAND EEPROM, it is necessary to apply a high erasure voltage (V.sub.EE) of about 20V to the p-well layer. Therefore, the conventional NAND EEPROM must use a transistor of a high withstand voltage (in which, the thickness of the gate oxide film is as thick as 400 .ANG.. In addition, as regards the design rule, the distance between lines must be greater as compared to the circuit for a lower voltage. For these reasons, element refinement and high-density integration of elements have been prevented.
Further, since a high voltage is used, it is difficult to design a reliable element.
Data Writing and Erasing
In data writing, a writing voltage Vpp (e.g., 20V) is applied to the control gate of a selected cell of the control gates CG. An intermediate voltage Vm (e.g., 10V) between Vpp and 0V is applied to the control gate of a non-selected cell. In this state, a potential of 0V is applied to the bit line BL of the cell to which data "0" is to be written, while the potential of Vm is applied to the bit line BL of the cell in which data "1" is to be maintained.
In a selected memory cell (the potential of the control gate=Vpp=20V, the potential of the bit line=0V), the voltage (Vpp=20V) applied between the control gate electrode 16 and the substrate 11 is divided in accordance with a ratio (hereinafter referred to as a coupling ratio) of a static capacitance (Cs1) between the floating gate electrode 14 and the semiconductor substrate to a static capacitance (Cs2) between the floating gate electrode 14 and the control gate electrode 16 (Cs2/(Cs1+Cs2)). For example, in the case of Cs2/(Cs1+Cs2)=0.5, the potential difference between the floating gate electrode 14 and the semiconductor substrate 11 is 10V. In this case, assuming that the thickness of the tunnel oxide film is 10 nm, the field of 10 MV/cm is applied to a gate oxide film (hereinafter referred to as a tunnel oxide film) between the floating gate electrode 14 and the semiconductor substrate 11. At this time, a Fowler-Nordheim current (hereinafter referred to as a tunnel current) flows through the tunnel oxide film, so that electrons are injected into the floating gate electrode 14. As a result, the threshold voltage of the selected memory cell becomes positive; that is, the normally-off state. In other words, data "0" is written into the selected cell. The threshold voltage of the selected cell should be set to a level between 0V and Vcc (e.g., 5V).
On the other hand, in a non-selected memory cell column wherein data "1" is maintained, although a certain field is applied to a memory cell, even when a high voltage (Vpp) is applied to the control gate electrode 16, the voltage applied between the substrate 11 and the control gate electrode 16 is smaller than that in the selected cell (Vpp-Vm=20V-10V=10V), since the voltage (Vm) from the bit line is applied to a channel. Thus, since the field applied to the tunnel oxide film is also mitigated (to about 5 MV/cm), no tunnel current flows and data "0" is not written into the non-selected cell.
In data reading, the bit line which is connected to the cell column including a selected cell is precharged to 1V for example, while the other bit lines are set to 0V. The voltage of 0V is applied to the control gate of the selected cell, while a voltage of Vcc (=5V) is applied to the control gates of all the non-selected cells. As a result, the selected cell is turned on or off depending on whether data "1" or "0" has been written therein. The non-selected cells are all in the ON state, whether data "1" or "0" has been written. Therefore, when the selection gates SG1 and SG2 are opened, if the selected cell has data "1", i.e., in the normally-on state (depleted), a current flows through the source. However, if the selected cell has data "0", i.e., in the normally-off state (enhanced), no current flows in the cell column. Thus, it is possible to determine whether the selected cell has data "0" or "1", depending on whether a current flows through the selected cell column from the bit line. FIG. 5 shows characteristics of a cell having a threshold voltage Vth higher than 0V (i.e., enhanced cell) and a cell having a threshold voltage Vth lower than 0V (depleted cell). In FIG. 5, V.sub.CG denotes a voltage applied to the control gate and Id denotes a drain current.
The data writing as described above is called a fixed-potential writing system. An improvement of the system is a self-boosting system published by K. D. Suh et al. in IEEE Journal of Solid-State Circuits, vol. 30, No. 11 (1995). In the self-boosting system, the write inhibit mechanism in a non-selected NAND cell column is improved, so that the potential amplitude between a selected bit line and a non-selected bit line is reduced to 0V.fwdarw.Vcc (e.g., 3.3V) from 0V.fwdarw.V.sub.M (e.g., 10V) in the conventional system. As a result, the withstand voltages of various transistors in the memory device can be lowered, thereby achieving element refinement.
Further, T. S. Jung et al. improved the self-boosting system of K. D. Suh et al. and devised a local self-boosting system (LBS), in which a cell is selectively self-boosted and data is written therein (T. S. Jung et al. ISSCC Tech-Dig., P32, 1996). According to the local self-boosting system, the stress due to a write voltage Vpgm in a non-selected NAND cell column can be reduced, so that the variance of the threshold voltages of multileveled cells in particular can be considerably reduced.
However, the local self-boosting system is disadvantageous in that the write inhibition in a non-selected NAND cell column does not have sufficient reliability, and data cannot be written at random in a plurality of cells in a selected NAND cell column.